1. Field of the Invention
The invention relates to designing integrated circuits and more particularly to optimization of circuit designs through sequential timing information.
2. Description of the Related Art
Traditional RTL-to-Layout synthesis has almost exclusively been focused on non-sequential optimization techniques. A design methodology based on fixed register and latch positions that uses a combination of static timing analysis, combinational synthesis, and formal equivalence checking generally provides an effective decomposition of the overall design problem into orthogonal issues which can be dealt with independently. In conjunction with techniques such as a standard-cell place-and-route approach, zero-skew clock distribution, and full or partial scan testing, such a methodology has proven to be robust and predictable, which stimulated broad adoption of the methodology. Complementary to the methodology's appeal from a modeling perspective, this partitioning also supports independent implementation and marketing of the individual components as point tools for which standardized interfaces provide the flexibility to adapt the flow for different needs.
In recent years, the boundaries between different design stages have become more blurred and increasingly integrated approaches have begun to dominate parts of the design methodology. This development is driven in part by the fact that a performance and area compromise made by a vertically partitioned flow does not scale proportionally for increasing chip sizes and shrinking device structures. For example, traditionally, logic synthesis and physical design have been performed by separate tools. In the past, a compact model for a logic function and delay calculation of the individual gates was sufficient to estimate and control the desired design characteristics in both applications. However, the growing chip density and size make abstract modeling of physical effects increasingly difficult. The evolution of a more integrated approach to logic and physical synthesis addresses, among other problems, the growing dominance of wire delays for the overall system performance.
Sequential optimization (SO) techniques have been researched for many years and there arena number of efficient approaches available that are applicable to practical designs. SO has the potential to significantly improve the performance, area, and power consumption of a circuit implementation to a degree that is not achievable with traditional combinational synthesis methods. SO techniques pertain in general to the staging and timing of provision of signals to combinational logic paths in a circuit design.
Sequential synthesis methods of practical interest are retiming, C. Leiserson and J. Saxe, “Optimizing synchronous system,” Journal of VLSI and Computer Systems, vol. 1, pp. 41-67, January 1983; C. Leiserson and J. Saxe, “Retiming synchronous-circuitry,” Algorithmica, vol. 6, pp. 5-35, 1991, and clock skew scheduling J. P Fishburn, “Clock Skew optimization,” IEEE Transcactions on Computers, vol. 39, pp. 945-951, July 1990. In both methods, the traditionally stated goal is to balance the path delays between registers and thus to maximize the performance of the design without changing its input/output behavior.
Retiming is a structural transformation that moves a registers in a circuit without changing the positions of the combinational gates. Changing register positions has the effect of changing the staging of signals in a design that is changing the location in the design relative to combinational logic paths in the design, at which signals are temporarily stored (i.e., registered). Of course, changing register positions also has the effect of changing the timing of provision of signals to combinational logic paths in the design. It is traditionally limited to designs with extremely high performance requirements, which are typically developed using a carefully crafted design and verification environment. One reason for a lack of widespread adoption of retiming has been an inability to accurately predict the impact of retiming at early design flow stages upon downstream design flow stages.
Clock skew scheduling preserves the circuit structure, but applies tuned delays to the register clocks—thus virtually moving them in time. Clock skew scheduling—or clock latency scheduling—has the effect of changing the timing of the provision of signals to combinational logic paths in the design. In recent years, clock skew scheduling has been adopted in some design flows as a post-layout optimization technique to reduce the cycle time, I. S. Kourtev and E. G. Friedman, Timing Optimization through Clock Skew Scheduling. Boston, Dortrecht, London Kluwer Academic Publisher, 2000, and the number of close-to-critical path, C. Albrecht, B. Korte, J. Schietke, and J. Vygen, “Cycle time and slack optimization for VLSI-chips,” in Digest of Technical Papers of the IEEE International Conference on Computer-Aided Design, pp. 231-238, November 1999.
SO techniques have found only limited acceptance in contemporary ASIC design flows, e.g. in pipeline-retiming during logic synthesis or clock skew scheduling for post-layout cycle-time improvement. SO techniques sometimes have been employed as point applications. That is, SO techniques have been applied to some point in a design flow rather than to the overall design. For instance, previously published work suggests retiming as a repeated point-application interleaved with combinational, synthesis (e.g. S. Malik, E. M. Sentovich, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Retiming and resynthesis, Optimizing sequential networks with combinational techniques,” IEEE Transactions on Computer-Aided Design, vol. 10, pp. 74-84, January 1991). However, computing suitable register positions is computationally expensive and actually not needed in early synthesis stages. Furthermore such limited usage may commit a design to a specific structure using only local information and missing a significant fraction of the sequential optimization space. An analysis of some ASIC designs suggests that although ordinarily only a small fraction of a given design is likely to be sequentially critical, combinational, timing analysis approaches do not reveal this information and thus traditional integrated circuit design techniques cannot take advantage of it.
Sequential optimization (SO) techniques have significant, potential to improve the performance of integrated circuit designs and/or decrease their size and power consumption. Despite a rich set of theoretical and practical work on retiming and clock skew scheduling, there has been a need for improved sequential timing analysis to ascertain an improved measure of sequential flexibility (i.e. sequential slack) in order to achieve better design optimization. There also has been a need, for improvement in the application of sequential flexibility to circuit design flow. The present invention meets these needs.